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STIL: a new component family for Inrush Current Limitation Circuit (ICLC)
Igor Bimbaud and Benoît Peron, ASDTM and Discrete Division, STMicroelectronics, Tours, France.
Abstract During the start up of an AC/DC power supply, the high current can raise up to 50 times the nominal current of the system. This inrush current can create a voltage drop in the main supply that may affect the operation of any equipment connected to the same power network and blow up the input wire fuse as well. In order to control this effect and limit the inrush current intensity, the two most commonly found solutions are either for lower power systems, the use of stand-alone impedance before the rectifier bridge or the use of serial impedance at the input shorted by a pass element (SCR, Triac or relay). Unfortunately none of these solutions are fully acceptable and fulfill the ideal expectation of the inrush current limitation circuit (ICLC). Based on its advanced ASDTM technology, STMicroelectronics is proposing a new circuit configuration and the associated component family, the STIL, which closely meets the requirements mentioned above. This article describes in detail this new circuit as well as the benefits brought by STIL and the ASDTM technology. 1. Introduction to the Inrush Current Limitation Circuit (ICLC)
All the front-ends of off-line power supplies are made with a bridge rectifier and a filter bulk capacitor as shown in figure 1. Fig. 1: Typical off-the-line AC/DC power supply.
Breaker Fuse Power source
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During start up, the charge of the bulk capacitor generates a surge current on the mains network, commonly called inrush current. If nothing is done to limit the level of this inrush current, the protection wire fuse of the power supply might blow up and the circuit breaker of the main power distribution might be forced to open.
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The immediate but not suitable design solution would be to oversize these serial protection devices; thus increasing the total system cost by reducing the responsiveness of the power failure protection circuits of the converter. Hence, power supply designers must introduce an ICLC on the front-end of the power supply to reduce this inrush current; however this ICLC should not affect the performance of the converter and should respond to the following expectations: a) Power losses reduction and no hot spot: the inrush current should not degrade the global efficiency of the power supply. It should also not generate an excessive local point of heat (hot spot) on the power printed circuit that might increase the operating temperature of the components and affect the reliability of the power supply. b) Responsiveness: the circuit should be able to instantly limit the inrush current during repetitive on / off cycles of the mains (a.c. on / off cycling). c) Robustness and immunity: the ICLC should be immune against power line disturbance that might be generated at turn-on of the power supply. d) Small size: the inrush current limitation circuit volume should be minimized in order to keep the power density (W/cm3) of the power supply high.
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2. Common circuits overview This section describes the operation of the different circuits commonly encountered to limit the inrush current and highlights the advantages and drawbacks of each of them. 2.1. Stand-alone serial impedance insertion Figure 2 shows the basic connection of an ICLC using stand-alone impedance in series before the rectifier bridge. This inrush resistor Rinrush is rated from a few ohms to approximately 10 . Fig. 2: ICLC using stand-alone resistor NTC. resistance remains not nil and significant losses can be recorded when the input RMS current increases. This may have an important impact on the efficiency of the converter (see figure 14) and may also generate a hot spot. The NTC is therefore well suited for medium power converters from 20 to 50W. However, when the power is above 70W and when the ambient temperature on the power circuit board reaches 60C or more, like in a closed adapter housing, the stand-alone NTC is no longer convenient. 2.2. Impedance shorted by a pass element In order to reduce the losses, it is possible in the ICLC to short the serial impedance with a pass element as soon as the bulk capacitor is charged and when the converter starts up. Three kinds of pass elements are commonly used. These are: the Silicon Pass Element (SPE), SCRs or triacs, the Electromechanical Pass Element (EPE) such as relays, the Half Controlled Rectifier Bridge (HCRB). These solutions are separately covered in the next sections. 2.2.1. Serial Silicon Pass Element (SPE) The triacs and SCRs are used for medium size opened frame or ventilated power supplies (see figure 3). The most typical applications are medium size servers, telecom power supplies and other kinds of converters with a power rating from 100W to around 350W. The SCR is mounted in series after the bridge while the triac is mounted before. In both cases, during the nominal state, the pass element is closed and the inrush resistor is shorted. In that operation mode the auxiliary power supply coupled on the boost choke of the PFC circuit drives the pass element. When the mains a.c. disappears, the PFC controller stops switching and the voltage Vs drops down; the pass element turns off. When the a.c. line recovers, the PFC controller turns on after the bulk capacitor has been partially recharged through the inrush resistor. The inrush current is then correctly limited. The output of the auxiliary power supply (Vs) raises up again, the SPE is triggered and shorts the inrush resistor Rinrush. Rinrush can then be replaced by an NTC, which is smaller than a resistor. Thanks to the shorting pass element, the NTC temperature is kept low and its resistance value high so that the ICLC is active even during the complete a.c. on / off cycle. However the inconvenience of the silicon pass element is the conduction losses added to the losses of the four diodes of the rectifier bridge (see figure 5).
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Rinrush N L Filter Bridge Main converter
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This simple and extremely cheap circuit is found in low power converters like battery chargers or low power open frame power supplies. When the RMS input current increases, the power dissipation of the resistor becomes too high and generates potential hot spots in nominal operating mode. Its use is therefore limited to power converters below 10W approximately. When the power rating increases, the use of a Negative Coefficient Temperature (NTC) resistor in place of a resistor is an alternative solution. The NTC has a lower size than the stand-alone resistor. At cold start, the NTC temperature is low (ambient temperature), therefore its equivalent resistance is sufficiently high to limit the inrush current. During normal operation, the input RMS current heats the NTC by Joule effect. Thus, its resistance decreases to a few milliohms. Although the NTC offers lower losses than a resistor, it cannot fulfill all the expectations of the ICLC as listed above. The major drawback of the stand-alone NTC is that the ICLC cannot remain active during the mains a.c. on / off cycling. Indeed, a few milliseconds after the first cold start-up of the converter, the NTC is already warm and if mains a.c. on / off cycles are applied, the elapsed time between the repetitive "on" events is not long enough to cool the NTC. During that period of time, the bulk capacitor is still not fully charged. Therefore, a high level inrush current may occur which can no longer be limited. Moreover when the NTC is warm, its
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Fig. 3: SPE and EPE circuits.
Relay TRIAC Vin Rinrush Bridge m SCR TRIAC Relay driver Vout Vs Vcoil IC C R Rinrush Relay SCR DinrushPFC
Fig. 4: Front-end power supply with a Half Controlled Rectifier Bridge (HCRB).
VR VMains D1 IRev1 IRev2 VRev1
SCR1 SCR2
DinrushPFC Rinrush D2 VRev2
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2.2.2. Electromechanical Pass Element (EPE) In order to reduce the losses generated by the shorting pass element, some ICLCs are made with an electromechanical relay (see figure 3) in place of the silicon device. The conduction losses are obviously negligible in comparison with the silicon element, however the inconvenience is mainly the size (more than 10mm long for a 15Amps relay) and secondly the low responsiveness of the component. Indeed the release time, which is the time between the coil voltage drop when it turns off and the actual contact opening, can be very long, above 20ms in some cases. This long reaction time necessary for opening makes the relay not suitable when the responsiveness after a.c. on / off cycling is expected. 2.2.3. Half Controlled Rectifier Bridge (HCRB) configuration A HCRB circuit is shown in figure 4. It consists to realize a rectification stage with two top SCRs, SCR 1 and SCR2 and two bottom diodes for the return (D3, D4). During start-up, the inrush current is deviated through the two top diodes (D1, D2) of the rectification bridge and is limited by the inrush resistor Rinrush. As soon as the bulk capacitor is charged, the PFC controller turns on. The auxiliary power supply coupled to the boost choke of the PFC boost converter (the same as figure 3) provides enough current energy to close SCR1 and SCR2. During the nominal operation, the a.c. input current is rectified by both SCRs and the two diodes D3 and D4 of the HCRB configuration. Moreover, top diodes D1 and D2 of the bridge, as well as inrush resistor Rinrush, are shorted. Ultimately, with the use of a traditional diode rectification bridge (D1, D2, D3, D4), this topology consists of connecting two SCRs in parallel with the diode rectification stage and the inrush resistor.
Compared to a serial configuration circuit SPE, the losses of the HCRB circuit are reduced by about the equivalent losses of two diodes in a traditional bridge diode. The graph presented on figure 5 compares the losses for a 1kW converter between SPE and HCRB solution. In this case, we can see that the losses due to the triac (SPE) and the SCRs of the HCRB are approximately the same. However, the losses in the rectification bridge are reduced in half with the HCRB circuit. The total losses reduction is about 14W, which represents an efficiency benefit of about 1%. Fig. 5: Front-end losses comparison for a 1kW converter between SPE and HCRB solutions.
40 30 20 10 0
SPE (Triacs) HCRB (SCRs) 4 diodes losses TRIACs losses SCRs losses
Pass element losses
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2 diodes losses
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3. Comparative evaluation of the different ICLCs Table1 gives an outlook of the advantages and the drawbacks of the four ICLCs described above. It can be noticed that the HCRB configuration presents numerous advantages: high efficiency, small size and on / off cycling responsiveness (AC line drop). The next section covers the special trade-offs to be taken into account in order to select the correct SCRs for the HCRB circuit configuration.
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Table 1: Primary performance between several ICLC types. ICLC type Resistor NTC SPE EPE HCRB Losses High Medium High Low Low comparison Size High Small Small High Small
load Irev Vrev + Igt I Vpeak Vin Vrev
Figure 7 and 8 show comparative leakage current measurements for two different kinds of SCRs:
Fig. 6: Reverse losses due to Ik.
Responsiveness (fig. 4 circuit) Yes No Yes No Yes
Igt-rev=f(Igt) Ik=Igt-rev+Irev
4. SCR trade-off for HCRB configuration SCRs can be classified in two principal families: Sensitive and Non-sensitive devices. Sensitive SCRs need a minimum gate triggering current of a few ten microamperes whereas non-sensitive ones require a gate triggering current in the range of several milliamperes. 4.1. Static dv/dt immunity Sensitive SCRs are not immune to dynamic voltage variations due to the bounces of the mechanical power switch. In other words, this kind of thyristor component can be closed without gate current in an uncontrolled way if a high dV/dt is applied across it. Non-sensitive SCRs can sustain a minimum dV/dt in the range of 200V/s while sensitive SCRs are limited to around 10V/s. In order to improve the robustness of sensitive SCRs, some external capacitive snubbers can be added between the gate and the cathode pin. This snubber deviates the parasitic current generated by the dV/dt noise voltage from the gate pin and hence avoids any unexpected triggering pulse. 4.2. Leakage reverse current losses In a common and simple manner, the SCRs of the HCBR are triggered by a constant current as shown on figure 6. In this kind of circuit, a reverse voltage (Vrev) is applied across the SCR at each half of the mains a.c. period (see figure 6). A reverse bias leakage current (Igt-rev) proportional to the gate current (Igt) flows from cathode to anode in the SCR. This current adds to the normal reverse leakage current Irev. Thus, the total reverse current Ik flowing through the SCR is equal to: (1) Ik = Igt-rev + Irev Assuming that the total reverse current is constant whatever the amplitude reverse voltage (Vrev), the reverse losses for one SCR can be given by: (2) Prev-loss= Vpeak. Ik / Where Vpeak is the peak voltage of the a.c. mains and Ik is the total reverse leakage current.
T
Sensitive SCR Non-sensitive SCR Each record shows the total leakage reverse current (Ik) (vertical axis) versus the reverse bias voltage (Vrev) applied across the SCR (horizontal axis) for different gate currents (Igt). Fig. 7: Sensitive SCR leakage reverse current (Ik) versus Vreg and Igt.
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Fig. 8: Non-sensitive SCR leakage reverse current (Ik) versus Vreg and Igt.
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One can see that for the same reverse voltage and with the associated gate triggering current, the leakage current of the Sensitive SCR (Ik=100A) is about 100 times lower than the non-sensitive SCR (Ik=9.2mA). Thus, the reverse losses of the Sensitive SCR are also about 100 times lower than with the non-sensitive SCR (see table 2). 4.3. Consequences Concerning the HCRB circuit, it appears that with sensitive SCRs, the total reverse losses become negligible. However, their sensitivity to static dV/dt make them non-suitable for that application: indeed, as it is detailed further in this paper, high static dV/dt is applied across the SCR at turn-on of the converter. This dV/dt can wrongly force the SCRs to close while the bulk capacitor is not still completely charged. A high inrush current can appear at that time. Therefore, it exists a trade-off between three parameters: static dV/dt, gate current (Igt), and reverse leakage current (Ik). The next section introduces a new technology that allows this trade-off to be solved. 5. Planar ASDTM technology The planar technology developed by STMicroelectronics is called ASDTM (Application Specific Discrete). An example of an ASDTM structure is shown on figure 9. Fig. 9: ASDTM structure. 6. Introduction of the new component STIL The ASDTM allows the integration of two unidirectional switches dedicated for the inrush current function. Based on HCRB configuration (see figure 10), ST has introduced a new ASDTM component family called STIL. The first products launched are the STIL02 and STIL04 (respectively 2 and 4Amps) that offer, on one hand a minimum static dV/dt beyond 500V/s at Tj=150C without snubber for a total pilot current of 20mA (for the two switches), and on the other hand its total reverse leakage current (Ik) doesn't exceed 300A (for one switch at Vrev = 400V at Tj=150C and Ipt1 = Ipt2 = 10mA) even with its pilot current triggering (figures 10 and 11). Fig. 10: STIL02 basic connection.
STIL
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Vrev (V) Ipt=6mA Ipt=8mA Ipt=10mA Ipt=12mA Ipt=14mA Ipt=16mA
Fig. 11: STIL02 leakage reverse current (Ik) versus Vrev and Ipt.
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7. Comparison between sensitive, non-sensitive SCR and STIL02 in the HCRB circuit
The ASDTM technology allows the monolithic integration of several power discrete and passive components (triac, SCR, diode, transistor and resistor). It is also a robust technology, which offers a solution for the trade-off described above. In other words, a SCR designed in the ASDTM technology can sustain a dV/dt about three times higher than a standard non-sensitive SCR with the same gate current rating at the same junction temperature.
7.1. Robustness: dV/dt immunity At the start-up of the converter, some oscillations appear at the front-end. They are extremely narrow. As shown in figure 12, these spikes are directly applied across the rectification bridge and create high dV/dt across the SCR of the HCRB. Therefore, if a too sensitive SCR is used, this dV/dt can force the SCR to close without control before the bulk capacitor is charged. In that case, the inrush current is not limited and the input wire fuse might blow up.
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Figure 13 presents the typical dV/dt immunity for the different types of SCRs. The dV/dt immunity of the sensitive SCRs is given with or without a snubber capacitor of 100nF connected between the gate and the cathode pin. With a snubber, the dV/dt immunity of the sensitive SCR reaches 120V/s. In any case, this sensitive SCR cannot be used in applications having parasitic spikes as shown in figure 12 where a dV/dt up to 280V/s has been recorded. The only choice is then to use a non-sensitive SCR or the STIL02/STIL04 devices, which are designed to offer a typical dV/dt above 1000V/s.
Fig. 12: Oscillation spike at start-up of the converter.
Voltage across the bridge at startup:VR
Narrow spike
7.3. Efficiency comparison Some comparative efficiency measurements have been carried out on the same 70W converter to illustrate the influence of the reverse gate current and the associated reverse power losses on the total performance of an off-line converter. The front-end of this converter was originally made with a stand-alone NTC in series with a diode bridge. The design has been modified to a HCRB configuration by keeping the original bridge diode as shown in figure 4. The efficiency has then been recorded for different system load values and with the three different thyristor technologies (non-sensitive, sensitive and planar ASDTM). The comparative results are shown in figure 14. This comparison shows that the HCRB circuit with STIL02 or sensitive SCR allows about 1.5 % efficiency to be gained at low line and high load conditions in comparison with a serial configuration using a stand-alone NTC.
Fig. 14: Efficiency comparison.
84 83 82
Magnified spike
dV/ dt =280V/s
Fig. 13: Typical dV/dt immunity comparison.
Static dv/dt versus SCRs and the STIL
10V/s Sensitive SCR Sensitive SCR (Cgk=100nF) with Snubber TYN808 STIL 120V/s
Vd=470V, Tj=125C, gate open
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7.2. Reverse power losses comparison Table 2 gives the losses related to the reverse leakage current for each type of SCR using equation (2). With the non-sensitive SCR, the reverse losses are nearly 900mW whereas with the ASDTM, the reverse losses are close to the sensitive SCR and about 90 times lower than with the non-sensitive SCR.
Sensitive Non-sentiv SCR e SCR Ploss-rev (mW)
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STIL-02 (HCRB)(Ipilot=12mA) NTC (stand-alone) Sensitive SCRs (HCRB)(Igt=100A) Non-sensitive SCRs (HCRB)(Igt=16mA)
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Moreover the influence of the reverse leakage current on the efficiency of the system is also highlighted: the non-sensitive bridge SCR and its high leakage reverse current reduces the efficiency by more than 2% whatever the line voltage and in high load conditions, when compared to the sensitive SCR bridge or the ASDTM technology.
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8. Conclusion An innovative inrush current limiting circuit configuration has been introduced. It consists of the connection of two unidirectional switches in parallel with the bridge and allows the reduction of the conduction losses when compared to a traditional serial architecture (silicon pass element and diode bridge). The trade-off of the SCR has been studied for this application as well as the features and benefits high dV/dt immunity and low reverse leakage current losses - brought by the ASDTM technology developed by STMicroelectronics for this application have been described.
References: [1] EPE'97 Trondheim Vol.1 Sept 97 "A methodology for the functional power integration" R.Pezzani - E. Bernier - C-Ballon
[2] STMicroelectronics Application note AN301 "The TRIAC" by M.Sauvanat - P.Rault
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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